\doxysection{FMC\+\_\+\+Bank2\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_c___bank2___type_def}{}\label{struct_f_m_c___bank2___type_def}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}


Flexible Memory Controller Bank2.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_a5bf7d23543197241fc3454bf4457f324}{PCR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_a457388fbdc292927afa844272ad00782}{SR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_aeb4961a8f61a4944138ca5bbb1475011}{PMEM2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_afceaece2981c4f5f2f78f32ee378bbc6}{PATT2}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_aaed86fc56cbd3f7f91966bdfa5752fe8}{RESERVED0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank2___type_def_a4a7f2a49c73fa3a30ee72d218a9c1d1b}{ECCR2}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Memory Controller Bank2. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_c___bank2___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_c___bank2___type_def_a4a7f2a49c73fa3a30ee72d218a9c1d1b}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!ECCR2@{ECCR2}}
\index{ECCR2@{ECCR2}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ECCR2}{ECCR2}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_a4a7f2a49c73fa3a30ee72d218a9c1d1b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+ECCR2}

NAND Flash ECC result registers 2, Address offset\+: 0x74 \Hypertarget{struct_f_m_c___bank2___type_def_afceaece2981c4f5f2f78f32ee378bbc6}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!PATT2@{PATT2}}
\index{PATT2@{PATT2}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PATT2}{PATT2}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_afceaece2981c4f5f2f78f32ee378bbc6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+PATT2}

NAND Flash Attribute memory space timing register 2, Address offset\+: 0x6C \Hypertarget{struct_f_m_c___bank2___type_def_a5bf7d23543197241fc3454bf4457f324}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!PCR2@{PCR2}}
\index{PCR2@{PCR2}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PCR2}{PCR2}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_a5bf7d23543197241fc3454bf4457f324} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+PCR2}

NAND Flash control register 2, Address offset\+: 0x60 \Hypertarget{struct_f_m_c___bank2___type_def_aeb4961a8f61a4944138ca5bbb1475011}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!PMEM2@{PMEM2}}
\index{PMEM2@{PMEM2}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PMEM2}{PMEM2}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_aeb4961a8f61a4944138ca5bbb1475011} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+PMEM2}

NAND Flash Common memory space timing register 2, Address offset\+: 0x68 \Hypertarget{struct_f_m_c___bank2___type_def_aaed86fc56cbd3f7f91966bdfa5752fe8}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_aaed86fc56cbd3f7f91966bdfa5752fe8} 
uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+RESERVED0}

Reserved, 0x70 \Hypertarget{struct_f_m_c___bank2___type_def_a457388fbdc292927afa844272ad00782}\index{FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}!SR2@{SR2}}
\index{SR2@{SR2}!FMC\_Bank2\_TypeDef@{FMC\_Bank2\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR2}{SR2}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank2___type_def_a457388fbdc292927afa844272ad00782} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank2\+\_\+\+Type\+Def\+::\+SR2}

NAND Flash FIFO status and interrupt register 2, Address offset\+: 0x64 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
